Three key materials for packaging technology of silicon carbide power devices - sintered silver

In the past 20 years, silicon carbide (SiC) has received increasing attention as a wide bandgap power device. The high frequency, high voltage, high temperature resistance, fast switching speed, and low loss characteristics of silicon carbide devices have led to higher efficiency and power density in power electronic systems.

Silicon carbide devicesThese excellent characteristics of silicon carbide power devices require efficient and highly reliable connections between power and signals through packaging and circuit systems in order to achieve perfect display, which also puts higher demands on the key packaging technologies of silicon carbide power devices. The following will summarize and outline the three key technical directions of low stray inductance packaging, high-temperature packaging, and multifunctional integrated packaging for silicon carbide power device packaging technology.

Low stray inductance packaging technology

Currently, most commercial SiC devices still use the packaging method of traditional Si devices. Traditional packaging technology is mature, low-cost, and compatible with and can replace existing Si based devices. However, traditional packaging structures result in large stray inductance parameters, causing severe voltage overshoot during the fast switching process of silicon carbide devices, as well as increased losses and electromagnetic interference.

The size of stray inductance is related to the area of the switching converter circuit. Among them, the metal bonding connection method, component pins, and the planar layout of multiple chips are the key influencing factors that result in the large area of traditional packaging converter circuits. Eliminating metal bonding wires can effectively reduce stray inductance values and control their magnitude below 5nH. Below, typical packaging structures will be introduced separately.

① Single tube flip chip packaging

The team from the University of Arkansas drew inspiration from BGA packaging technology and proposed a single tube flip chip packaging technique. This package flips the back electrode of the chip to the same plane position as the front electrode through a metal connector, and then places solder balls on the corresponding electrode positions, eliminating metal bonding wires and pin terminals. Compared to the TO-247 package, the volume has been reduced by 14 times and the on resistance has been reduced by 24%.

② DBC PCB hybrid packaging

The copper coated ceramic board (DBC) used in traditional module packaging limits the chip layout to only a two-dimensional plane, resulting in a large current loop area and high stray inductance parameters. However, combining the DBC process with the PCB board, using metal bonding wires to connect the surface of the chip to the PCB board, and controlling the commutation circuit between the PCB layers greatly reduces the current circuit area, thereby reducing stray inductance parameters. This hybrid packaging can control stray inductance below 5nH and reduce the volume by 40% compared to traditional modules

▲ DBC PCB Hybrid Packaging ▲

Flexible PCB board combined with sintered silverThe packaging method of the process is also used in commercial modules. Using flexible PCB board instead of bonding wire to achieve electrical connection between the upper and lower surfaces of the chip, the parasitic inductance of the internal circuit of the module is only 1.5nH, the switching speed is greater than 50kV/s, and the loss can be reduced by 50% compared to traditional modules.

This hybrid packaging method combines the advantages of two mature processes, is easy to manufacture, can achieve low stray inductance, and has a smaller volume. But the existence of PCB boards limits the reliability of high-temperature operation of the above packaging methods

③ Front side planar interconnect packaging of chips

In addition to using flexible PCB boards instead of metal bonding wires, planar interconnect connections can also be used to achieve the connection of the front side of the chip. The planar interconnection method not only reduces current loops, thereby reducing stray inductance and resistance, but also has better temperature cycling characteristics and reliability.

The embedded packaging used for SiC chips can also be considered as a planar direct connection packaging on the front of the chip. This method places the chip in a ceramic positioning groove, fills the gap with insulating medium, and finally covers both sides of the mask by sputtering metal copper to achieve electrode connection. By selecting appropriate packaging materials, the interlayer thermal stress of the module at high temperatures has been reduced, and the forward and reverse characteristics of the module can be measured at a high temperature of 279 ℃.

▲ Embedded packaging ▲

The planar direct connection packaging process expands the current circuit from the DBC board planar layout to the interlayer layout of the chip upper and lower planes by eliminating metal bonding wires, significantly reducing the circuit area and achieving low stray inductance parameters. The basic idea of achieving low stray inductance is the same as the double-sided heat dissipation packaging and three-dimensional packaging introduced later, but the implementation method is slightly different.

④ Double sided heat dissipation packaging technology

Due to its ability to dissipate heat on both sides and small size, double-sided packaging technology is commonly used for the packaging of IGBTs inside electric vehicles. The double-sided heat dissipation packaging SiC module uses DBC boards for soldering on both the upper and lower surfaces, allowing for simultaneous heat dissipation on both surfaces.

The difficulty of this process is that the upper surface of the chip needs to be sputtered or electroplated to make it weldable, and metal gaskets, connecting posts, etc. are added on the upper surface of the chip to eliminate the height difference of chips at different heights in the same module. In addition, SiC chips generally have small surface areas, and ensuring the welding quality within a limited area on the upper surface is the key to this process. Thanks to the symmetrical wiring of the upper and lower DBCs and a reasonable chip layout, this package can reduce the parasitic inductance parameters of the circuit to below 3nH, and the module thermal resistance is reduced by 38% compared to traditional packages.

⑤ Three dimensional (3D) packaging technology

The 3D packaging technology utilizes the vertical structural characteristics of SiC power devices, directly stacking the lower tube of the switch bridge arm on top of the upper tube, eliminating excess wiring at the midpoint of the bridge arm, and reducing the parasitic inductance of the circuit to below 1nH. The surface of the chip is first treated with copper plating, and then the chip electrodes are led out through through-hole copper deposition process. Finally, a multi-layer structure is completed by laminating PCB. Thanks to the busbar structure of the PCB, the module circuit inductance is only 0.25nH, and the Kelvin connection of the gate can be achieved simultaneously. The power density of this package is extremely high, and ensuring chip temperature control is a major challenge. The thickness of the outer copper layer and the surface heat convection coefficient have a significant impact on chip heat dissipation. In addition to power chips, passive components such as magnetic cores and capacitors can be embedded in PCBs in appropriate ways to improve power density.

From the above new structure, it can be seen that in order to fully utilize the advantages of SiC devices, improve power density, and eliminate metal bonding wire connections, it is a trend. By adopting various new structures, reducing the parasitic inductance value of module circuits and decreasing the volume is the guarantee for advancing power electronics towards high frequency, high efficiency, and high power density.

High temperature packaging technology

Copper wire can be used instead of aluminum wire for chip front connection, eliminating the difference in thermal expansion coefficient between bonding wire and DBC copper layer, greatly improving the reliability of module operation. In addition, the connection processes of aluminum and copper strips are expected to provide better solutions for silicon carbide due to their greater current interception ability, better power cycling, and heat dissipation capability.

Tin foil or solder paste is commonly used for connecting chips and DBC boards. The soldering technology is very mature and simple. By adjusting the solder composition ratio, improving the solder paste printing technology, reducing the void rate through vacuum soldering, and adding reducing gases, high-quality soldering processes can be achieved. However, the thermal conductivity of solder is low and varies with temperature, making it unsuitable for SiC devices to operate at high temperatures. In addition, the reliability issue of the solder layer is also a major cause of module failure.

▲ Comparison of typical soldering and sintering materials ▲

The sintered silver connection technology, with its extremely high thermal conductivity, low sintering temperature, high melting point and other advantages, is expected to replace soldering as a new connection method for SiC devices. The silver sintering process usually involves mixing silver powder with organic solvents to form silver solder paste, printing it onto a substrate, removing the organic solvent through preheating, and then pressing and sintering to achieve the connection between the chip and the substrate. One method to reduce the sintering temperature is to increase the pressure applied during sintering, but this also increases the corresponding equipment cost and can easily cause chip damage; Another method is to reduce the volume of silver particles, such as usingnano silverHowever, the cost of particle processing is high, so many studies continue to focus on micro silver particles to obtain suitable sintering temperature, pressure, and time parameters to achieve more ideal sintering effects.

In addition, to ensure the stable operation of silicon carbide devices, ceramic substrates and metal substrates also need to have good high-temperature reliability. The greater the difference in thermal expansion coefficients between different materials, the higher the interlayer thermal stress and the lower the reliability. So choosing materials with high thermal conductivity, thermal expansion coefficient values similar to silicon carbide materials is the key to improving packaging reliability.