How to solve the heat dissipation problem of chip packaging

Placing multiple chips in the same package can alleviate thermal issues, but as the company delves deeper into chip stacking and denser packaging to improve performance and reduce power, they are struggling with a range of new heat related problems.

Advanced packaged chips can not only meet the needs of high-performance computing, artificial intelligence, and power density growth, but also make the heat dissipation problem of advanced packaging more complex. Because hotspots on one chip can affect the heat distribution of neighboring chips. The interconnection speed between chips is also slower in modules than in SoCs.

John Parry, the head of the electronics and semiconductor industry at Siemens Digital Industrial Software, said, "Before the world entered multi-core and other fields, you were facing a chip with a maximum power of about 150 watts per square centimeter, which was a single point heat source. You could dissipate heat in all three directions, so you could achieve some quite high power density. However, when you have a chip, place another chip next to it, and then place another chip next to it, they will heat up to each other. This means you cannot tolerate each chip having the same power level, which makes the thermal energy challenge even more difficult.

This is one of the main reasons for the slow progress of 3D-IC stacking in the market. Although this concept makes sense from the perspective of power efficiency and integration - running well in 3D NAND and HBM - it's another matter when logic is included. Logic chips generate heat, and the denser the logic, the higher the utilization rate of processing components, and the greater the heat. This makes logical stacking rare, which explains the popularity of 2.5D flip chip BGA and fan out design (see Figure 1).

01 Choose the correct packaging

For chip designers, there are various packaging methods available. But the performance of chip integration is crucial. Silicon TSV、 Copper pillars and other components have different coefficients of thermal expansion (TCE), which affects assembly yield and long-term reliability.

If you want to open and close at a higher frequency, you may encounter thermal cycling issues. Printed circuit boards, solder balls, and silicon all expand and contract at different speeds. Therefore, it is normal to see thermal cycling faults in the corners of the package, where the solder balls may crack. Therefore, people may install additional grounding wires or power sources there.

The currently popular inverted BGA package with CPU and HBM has an area of approximately 2500 square millimeters. Mike McIntyre, Head of Software Product Management at Onto Innovation, said, "We see that a large chip can become four or five small chips. So we have to have more I/O to make these chips communicate with each other. So you can allocate heat.

Ultimately, heat dissipation is a problem that can only be addressed at the system level, accompanied by a series of trade-offs.

In fact, some devices are so complex that it is difficult to easily replace them in order to customize these devices for specific field applications. That's why many advanced packaging products are used for very large quantities or price flexible components, such as server chips.

Progress in Simulation and Testing of 02 Chip Modules

Nevertheless, engineers are seeking new methods to conduct thermal analysis of packaging reliability before manufacturing packaging modules. For example, Siemens provided an example of a dual ASIC based module that installs a fan out redistribution layer (RDL) on a multi-layer organic substrate packaged in BGA. It uses two models, one for WLP based on RDL and the other for BGA on multi-layer organic substrates. These packaging models are parameterized, including substrate layer stacking and BGA before introducing EDA information, and enable early material evaluation and chip placement selection. Next, EDA data is imported, and for each model, the material map can provide a detailed thermal description of the copper distribution in all layers. The final heat dissipation simulation (see Figure 2) considered all materials except for the metal cover, TIM, and bottom filling material.

JCET Technical Marketing Director Eric Ouyang, along with engineers from JCET and Meta, compared the thermal performance of single-chip chips, multi chip modules, 2.5D plug-in boards, and 3D stacked chips with one ASIC and two SRAMs. Apple's comparison with Apple keeps the server environment, heat sink with vacuum chamber, and TIM unchanged. In terms of heat, 2.5D and MCM perform better than 3D or single-chip chips. Ouyang and colleagues from JCET designed a resistance matrix and power envelope diagram (see Figure 3) that can be used in early module design to determine whether the input power levels and set junction temperatures of different chips can be reliably combined before time-consuming thermal simulations. As shown in the figure, a secure area highlights the power range that meets reliability standards on each chip.

Ouyang explained that during the design process, circuit designers may have a concept of the power levels of various chips placed in the module, but may not know if these power levels are within the reliability range. This diagram determines the safe power area for up to three chips in a small chip module. The team has developed an automatic power calculator for more chips.

03 Quantitative thermal resistance

We can understand how heat is conducted through silicon chips, circuit boards, adhesives, TIMs, or packaging covers, while using standard methods such as temperature difference and power function to track temperature and resistance values.

JCET's Ouyang said, "The thermal path is quantified by three key values - the thermal resistance from the device node to the environment, the thermal resistance from the node to the shell [at the top of the package], and the thermal resistance from the node to the circuit board. He pointed out that at least JCET's customers need θ ja, θ jc, and θ jb, which they then use in system design. They may require a given thermal resistance not to exceed a specific value and demand that the packaging design provide that performance. (See JEDEC's JESD51-12, Guidelines for Reporting and Using Encapsulated Thermal Information).

Thermal simulation is the most economical method for exploring the selection and matching of materials. By simulating the working state of the chip, we usually discover one or more hotspots, so we can add copper to the substrate below the hotspots to facilitate heat dissipation; Or change the packaging material and add a heat sink. The system integrator may specify that the thermal resistances θ ja, θ jc, and θ jb must not exceed certain values. Normally, the temperature of silicon nodes should be kept below 125 ℃.

After the simulation is completed, the packaging factory conducts experimental design (DOE) to obtain the final packaging solution.

04 Choose TIM

In the packaging, more than 90% of the heat is dissipated from the top of the chip to the heat sink through the packaging, usually using vertical fins based on anodized aluminum. A thermal interface material (TIM) with high thermal conductivity is placed between the chip and the package to help transfer heat. The next generation TIM for CPUs includes metal sheet alloys such as indium and tin, as well as silver sintered tin, with conductivities of 60W/m-K and 50W/m-K, respectively.

As manufacturers transition from SoC to chiplet technology, there is a need for more TIMs with different properties and thicknesses.

Young Do Kweon, Senior R&D Director at Amkor, stated that for high-density systems, the thermal resistance of TIM between the chip and the package has a greater impact on the overall thermal resistance of the package module. The power trend is rapidly increasing, especially for logic, so we focus on maintaining low junction temperatures to ensure reliable semiconductor operation. Although TIM suppliers provide thermal resistance values for their materials, in reality, the thermal resistance (θ jc) from the chip to the package is influenced by the assembly process itself, including the bonding quality and contact area between the chip and TIM. He pointed out that testing with actual assembly tools and adhesive materials in a controlled environment is crucial for understanding the actual thermal performance and selecting the best TIM for customer identification.

Gap is a special issue. The use of materials in packaging is a big challenge, "said Parry from Siemens." We already know that the material properties of adhesives or glues, as well as the way materials wet the surface, can affect the overall thermal resistance of the material, that is, the contact resistance. This largely depends on how the material flows into the surface without producing defects. If there are any missing areas that are not filled with glue, it will cause additional resistance to heat flow

05 Dealing with heat issues in different ways

Chip manufacturers are trying their best to solve the heat dissipation problem. Randy White, the project manager of Keysight Technologies' memory solutions, said, "The packaging method remains the same. If you reduce the chip size by a quarter, the speed will increase. This may result in some signal integrity differences. Because the bonding wires of the external packaging will enter the chip, the longer the wire, the larger the inductance, so there is an electrical performance part. So, how to consume so much energy in a small enough space? This is another key parameter that needs to be studied

This has led to a significant investment in cutting-edge bonding research, seemingly focused on hybrid bonding. However, the cost of hybrid bonding is high and it is still limited to applications with high-performance processors. TSMC is currently one of the only companies offering this technology. However, the prospect of combining photons on CMOS chips or silicon-based gallium nitride is very promising.

Conclusion 06

The initial concept of advanced packaging is that it will work like Lego bricks - chips developed at different process nodes can be assembled together, and thermal problems will be alleviated. But this comes at a cost. From the perspective of performance and power, the distance over which signals need to propagate is crucial, and keeping circuits always on or partially open can affect thermal performance. Splitting chips into multiple parts to increase production and flexibility is not as simple as it seems. Every interconnect in the package must be optimized, and hotspots are no longer limited to a single chip.